1. Field of the Invention
This invention relates to a comparator circuit that compares a pair of differential input signals.
2. Description of the Related Art
It is a common practice in recent years to transmit high frequency signals in a form of differential signals in order to suppress an influence of noise or the like. A comparator is generally used as an interface when an LSI receives such differential signals. When a USB cable is connected to a microcomputer, for example, the microcomputer is provided with an interface having a comparator as disclosed in Japanese Patent Publication No. 2002-149626.
FIGS. 4A and 4B are circuit diagrams showing a comparator according to a prior art. The comparator is composed of a pair of N-channel type differential MOS transistors MN1 and MN2, a pair of P-channel type MOS transistors MP1 and MP2 connected in a form of a current mirror and a constant current source 1, as shown in FIG. 4A. A gate of the differential MOS transistor MN1 makes a positive input terminal 2, a gate of the differential MOS transistor MN2 makes a negative input terminal 3, a connecting node between MP2 and MN2 makes a positive output terminal 4, and a connecting node between MP1 and MN1 makes a negative output terminal 5. The circuit expressed in a circuit symbol is shown in FIG. 4B. The comparator described above is hereafter referred to as “an N-type comparator” for the sake of convenience.
Since this circuit uses the pair of N-channel type differential MOS transistors MN1 and MN2 as differential transistors, when a differential input voltage Vin is close to Vss, more specifically when Vin<Vtn+α, a source-drain impedance of each of the differential MOS transistors MN1 and MN2 becomes so high that the circuit operates only at reduced rate or halts the operation. Here, Vtn is a threshold voltage of each of the pair of N-channel type differential MOS transistors MN1 and MN2 and α stands for a change in the threshold voltage Vtn due to a back-gate bias effect. Therefore, the input voltage to the comparator is limited within a range from Vtn+α to Vdd.
FIGS. 5A and 5B are circuit diagrams showing another comparator according to a prior art.
This comparator is composed of a pair of P-channel type differential MOS transistors MP11 and MP12, a pair of N-channel type MOS transistors MN11 and MN12 connected in a form of a current mirror and a constant current source 10, as shown in FIG. 5A. A gate of the differential MOS transistor MP11 makes a positive input terminal 12, a gate of the differential MOS transistor MP12 makes a negative input terminal 13, a connecting node between MP12 and MN12 makes a positive output terminal 14, and a connecting node between MP11 and MN11 makes a negative output terminal 15. The circuit expressed in a circuit symbol is shown in FIG. 5B. The comparator described above is hereafter referred to as “a P-type comparator” for the sake of convenience.
Since this circuit uses the pair of P-channel type differential MOS transistors MP11 and MP12 as differential transistors, when a differential input voltage Vin is close to Vdd, more specifically when Vin>Vdd−Vtp−β, a source-drain impedance of each of the differential MOS transistors MP11 and MP12 becomes so high that the circuit operates only at reduced rate or halts the operation. Here, Vtp is a threshold voltage of each of the pair of P-channel type differential MOS transistors MP11 and MP12 and β stands for a change in the threshold voltage Vtp due to a back-gate bias effect. Therefore, the input voltage to the comparator is limited within a range from Vss to Vtp+β.
Normal operation of the comparator described above is guaranteed only for the input voltage within the range from Vtn+α to Vdd or the range from Vss to Vdd−Vtp−β. Therefore, the comparators do not meet a device design requiring a wide input voltage ranging from Vss to Vdd.